RITENBR=NO_EFFECT_ON_DEBUG, RITINT=NO_MASK, RITEN=TIMER_DISABLED_, RITENCLR=NOT_CLEAR_ON_0
Control register.
| RITINT | Interrupt flag 0 (NO_MASK): The counter value does not equal the masked compare value. 1 (MASK): This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect. |
| RITENCLR | Timer enable clear 0 (NOT_CLEAR_ON_0): The timer will not be cleared to 0. 1 (CLEAR_ON_O): The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers. This will occur on the same clock that sets the interrupt flag. |
| RITENBR | Timer enable for debug 0 (NO_EFFECT_ON_DEBUG): Debug has no effect on the timer operation. 1 (HALT_ON_DEBUG): The timer is halted when the processor is halted for debugging. |
| RITEN | Timer enable. 0 (TIMER_DISABLED_): Timer disabled. 1 (TIMER_ENABLED): Timer enabled. This can be overruled by a debug halt if enabled in bit 2. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |